FULLY REMOTE Design Verification Engineer- System Verilog, UVM

If you are a FULLY REMOTE Design Verification Engineer- System Verilog, UVM, with experience, please read on!

What You Will Be Doing

• Create different functional test cases to validate independent design IP
• Develop test environment for integrating digital core with rest of the Integrated Circuit.. Creating functional
  

test cases to validate the design.

• Build and develop system level stress or corner cases to validate the functionality of the design,
• Create different power-up and initialization sequences for the different modes.
• Monitor the IC initialization and data flow using external memory model.
• Run functionality checks using the parasitic delays extracted for post layout gate level netlist.
• Integrate and compile core design and analog Verilog model on a FPGA. Emulating design for the pre-silicon
  

design verification & firmware development

Qualifications

• Skills in ASIC / FPGA verification (directed test or SystemVerilog / UVM)
• Basic knowledge in design techniques Verilog or VHDL
• Good knowledge of simulation flow
• Good basis in scripting Python, Perl, Bash
  

What You Need for this Position

• System Verilog
• UVM
• ASIC
• Design Verification Engineer
• DV
  

What's In It for You

Salary: $160K-$250K/yr

• Medical insurance
• Dental insurance
• Vision insurance
• 401(k)
• PTO/ Vacation
  

Benefits

• Vacation/PTO
• Medical
• Dental
• Vision
• 401k
  

So, if you are a FULLY REMOTE Design Verification Engineer- System Verilog, UVM, with experience, please apply today!

Email Your Resume In Word To

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Anya.Glover@

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